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| 001 | 1861 | ||
| 003 | AVIT | ||
| 005 | 20211120080814.0 | ||
| 008 | 080822s1998 ||||||||||||||||| ||und|d | ||
| 020 | _cINR 5424.00 | ||
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_2[Excel file from AVIT] _a7079 _qserial no |
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_aAVIT _cIN-KoLT |
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| 100 |
_aRushton Andrew _eaut |
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| 245 | 0 |
_aVHDL FOR LOGIC SYNTHESIS _cRushton Andrew |
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| 250 | _aSECOND | ||
| 260 |
_bJohn Wiley & Sons _c1998 |
||
| 650 | _aElectronics | ||
| 653 | _aLOGIC SYNTHESIS | ||
| 653 | _aOthers | ||
| 653 | _aVHDL | ||
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_2dcc _cBK |
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_c57569 _d57569 |
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